1. Field of the Invention
The present invention relates to a very small, high-speed bipolar transistor in which base and emitter regions are self-aligned and which is used for a high-performance integrated circuit.
2. Description of the Related Art
A high-performance bipolar transistor is widely used for digital integrated circuit (IC) elements such as high-speed arithmetic processors, memories, and the like, and analog IC elements such as arithmetic amplifiers, comparators, and the like. In order to achieve high integration and high-speed operation of a bipolar IC, a bipolar transistor must be micronized in both lateral and longitudinal directions. As one micronization technology in the longitudinal direction of a bipolar transistor, a polysilicon-emitter technology using a polysilicon film as a doping source for a shallow emitter is widely used. For micronization in the lateral direction of a bipolar transistor, various self-alignment technologies for self-aligning a base and emitter using a two-layered polysilicon film have been proposed (e.g., (1) IEEE Transactions on Electron Devices, Vol. ED-33, No. 4, Apr. 1986, p. 57, (2) Japanese Patent Disclosure (Kokai) No. 58-7862, (3) ISSCC 87, 1987, p. 58, and the like). Cut-off frequencies of bipolar transistors obtained by these self-alignment technologies are about to reach 30 GHz.
However, the self-alignment technologies of the bipolar transistor proposed so far have the following problems.
First, a high-concentration emitter layer and a high-concentration external or draft base layer are formed very close to each other. For this reason, the breakdown voltage of a base-emitter junction is significantly decreased, and the capacitance of the base-emitter junction is increased. If the emitter layer and the external base layer are formed sufficiently separate from each other so as to solve this problem, the base resistance is increased, and high-speed operation is disturbed.
Second, if the emitter width is decreased to a sub-micron order, a decrease in current gain or cut-off frequency is observed. This will be described in detail below with reference to FIGS. 11A to 11C. In these drawings, a p-type active base layer 22 and a p.sup.+ -type external base layer 23 are formed in a wafer on which an n-type collector layer 21 is formed. An n.sup.+ -type emitter layer 24 is self-aligned in these base layers. A first polysilicon film 25 serves both as a doping source of the external base layer 23, and as a base electrode, and a second polysilicon film 26 serves both as a doping source for an emitter layer, and as an emitter electrode. These polysilicon films 25 and 26 are isolated by an oxide film 27. The emitter layer 24 is formed not by a method of directly doping an impurity in a wafer exposed surface but by a method wherein after a polysilicon film 26 is deposited and arsenic ions are doped in the film 26 by ion implantation, the doped arsenic ions are shallow diffused in the wafer by annealing. However, with this method, according to the experiments of the present inventors, a high current gain and cut-off frequency can be obtained only until an emitter width equals 0.8 .mu.m. If the emitter width becomes smaller than 0.8 .mu.m, these characteristics are greatly decreased. Broken curves in FIGS. 8 and 9 represent these data. The decreases in characteristic are caused for the following reason. If an opening for forming an emitter layer is decreased to as small as 0.4 .mu.m, the film thickness t1 of the second polysilicon film 26 essentially becomes 1.5 to 2 times the thickness t1, i.e., a film thickness t2 in the emitter opening portion forming a narrow recess portion. In this state, even if ion implantation and annealing are performed in the second polysilicon film 26 under the same conditions as those when a sufficient emitter opening is formed, as shown in FIG. 11A, since the film thickness of the film 26 in the emitter opening portion is large, a predetermined emitter diffusion depth cannot be obtained. If the thickness of the preformed active base layer 22 is the same as that in FIG. 11A, the effective base width is increased as the emitter diffusion depth is decreased in FIG. 11B. If the film thickness of the second polysilicon film 26 is decreased, the film 26 can have an almost constant film thickness in a narrow emitter opening as in FIG. 11C. However, with this structure, since an effective emitter opening width b is very small relative to a diffusion emitter opening width a, as shown in FIG. 11C, a predetermined emitter diffusion layer cannot be obtained. A thick portion of the second polysilicon film 26 formed on the side walls of the opening does not serve as an effective impurity doping source even if an impurity is doped by ion implantation in its surface portion. As the opening width a is decreased, the ratio b/a of the effective opening width b to the opening width a is decreased. Therefore, under the same ion-implantation and annealing conditions as those when the opening width is large, a predetermined emitter diffusion depth cannot be obtained. As a result, in both FIGS. 11B and 11C, an impurity having a concentration necessary for the emitter region cannot be supplied by the conventional polysilicon-emitter technology.
A variation in characteristics depending on an emitter width is very disadvantageous for a bipolar IC in which a plurality of elements are formed with different emitter widths. For example, in order to obtain an emitter layer diffusion depth necessary for an internal circuit portion constituted by small elements each having an emitter width of about 0.5 .mu.m, the emitter layer diffusion depth becomes too large in an element such as an I/O buffer region having a large emitter width, resulting in a decrease in breakdown voltage.
Third, in the prior art, the active base layer and the emitter layer are self-aligned. However, the external base layer and the emitter layer are not self-aligned. More specifically, in FIG. 11A, the first polysilicon film 25 serving both as the doping source for the external base layer and as the base electrode is patterned to form an opening for forming the active base and the emitter. If mask misalignment occurs in this case, the external base layers formed on two sides of the emitter layer have different widths. This causes a variation in element characteristics.
Fourth, when a polysilicon film as a portion of a base electrode is patterned without using photolithography, a decrease in film thickness of the polysilicon film occurs. This problem will be described below with reference to FIGS. 12A and 12B. In this step, as shown in FIG. 12A, a predetermined recess portion is formed on a wafer 11 by an insulating film 12, and a polysilicon film 13 is deposited thereon. A photoresist 14 is coated to substantially flatten the surface of the resultant structure. Thereafter, the entire surface of the resultant structure is etched by dry etching to leave the photoresist 14 in only the recess portion. The polysilicon film 13 is etched by dry etching using the photoresist 14 as a mask so as to bury the polysilicon film 13 in the recess portion, as shown in FIG. 12B. However, in dry etching such as reactive ion etching, selectivity between the photoresist 14 and the polysilicon film 13 does not become high even if various conditions are properly selected. As a result, when the polysilicon film 13 on a stepped portion of the insulating film 12 is etched, the photoresist 14 is removed by etching at the same time, and the film thickness of the polysilicon film 13 to be buried is decreased, as shown in FIG. 12B.